The present invention relates generally to the field of processor and in particular to a method of correcting erroneous pre-decoded data associated with an instruction by forcing a branch correction procedure with a target address of the instruction.
Microprocessors perform computational tasks in a wide variety of applications. Improved processor performance is almost always desirable, to allow for faster operation and/or increased functionality through software changes. In many embedded applications, such as portable electronic devices, conserving power is also an important goal in processor design and implementation.
Most modern processors may employ a pipelined architecture, where sequential instructions are overlapped in execution to increase overall processor throughput. Maintaining smooth execution through the pipeline is critical to achieving high performance. Most modern processors also utilize a hierarchical memory, with fast, on-chip cache memories storing local copies of recently accessed data and instructions. One pipeline optimization technique known in the art is pre-decoding instructions. That is, instructions are examined as they are read from memory, are partially decoded, and some information about the instructions—known as pre-decode information—is stored in a cache memory along with the associated instructions. When the instructions are later fetched from the cache, the pre-decode information is also fetched, and used to assist in fully decoding the instructions.
Occasionally, the pre-decode information contains errors. These errors may be detected during decode stages in the pipeline. When an error is discovered, an exception occurs, and the pipeline must be flushed and all instructions, including the erroneously pre-decoded instruction, must be re-fetched. This process incurs significant performance and power management degradation.